This invention relates to multilayer ceramic integrated circuit packages; and more particularly, it relates to methods and apparatus for forming holes in the unfired layers of such packages during their fabrication.
Integrated circuits are conventionally fabricated on thin flat semiconductor chips which are about five to fifteen millimeters across and about one millimeter thick. These chips are quite fragile; and consequently, they are usually encapsulated in a package to protect them from damage. Such an integrated circuit package also contains conductors which contact microscopic bonding pads on the chip and thereby provide a means for sending electrical signals to and receiving electrical signals from the chip.
A conventional process for making multilayer ceramic integrated circuit packages is illustrated in FIGS. 1A, 1B, and 1C. Initially, a sheet of unfired ceramic is cut with a punch to form a part 10 of FIG. 1A. Part 10 is rectangular in shape, and it has several tooling holes 11. Thereafter, the part 10 is aligned under a second punch by means of the tooling holes 11; and it punches many small via holes 12 in the part. This results in part 10' as is shown in FIG. 1B. Subsequently, the part 10' is positioned under a third punch by means of the tooling holes 11, and it punches a central aperture 13 in the part. This results in part 10,, as is shown in FIG. 1C.
Part 10'' is just one layer of a complete integrated circuit package; and typically, the package will have from four to sixteen layers. All of the steps of FIGS. 1A-1C are repeated for each of the upper layers of the package, and the steps of FIGS. 1A-1B are repeated for the lower layers.
After the parts 10' and 10'' are formed, the via holes 12 are filled with a conductive ink. Next, patterned conductive traces are screened on them. Then, the parts are arranged in a stack in which the tooling holes 11 are utilized to align the various layers. This stack is then compressed and "fired" at a temperature of about 80% of the melting temperature of the powder in the layers, which causes the powder to sinter and agglomerate. Then, to complete the package, an integrated circuit chip is placed in the aperture 13; wire bonds are made between the chip and the conductive traces around the perimeter of aperture 13; and a lid is sealed over the aperture.
This process has been used in the prior art to make millions of integrated circuit packages. However, the process does have several limitations which are very serious for certain types of packages. In particular, as the diameter of the via holes 12 becomes smaller and smaller, the punches which form those holes become weak and break. Thus, as a practical matter for a high volume production operation, the punched via holes 12 have a minimum diameter of about 10 mils.
Also, as the total number of via holes 12 on a part 10' or 10'' increases, the corresponding punch becomes more difficult to make and thus more expensive. This added expense is multiplied by the number of layers in the package since each layer has a different via hole pattern and thus requires a different punch. Further, unfired ceramic is a very abrasive material, and thus the punches wear out. So in a production environment, the total number of via holes in any one punched part is limited to about 300.
Further, when the tooling holes 11 are used to position the parts 10' and 10'' during the punching operations of FIGS. 1B and 1C, those holes 11 become slightly stretched. These stretched holes will cause the parts to become misaligned when they are subsequently arranged in a stack. In turn, the misalignment can cause a short circuit or an open circuit between a filled via hole of one layer and a conductive trace on an adjacent layer. Such defects are not repairable, and so just one defect will cause the package to be scrapped.
Accordingly, a primary object of the invention is to provide an improved method of fabricating multilayer integrated circuit packages in which all of the above problems are overcome.